vlnv (![[info]](http://l-stat.livejournal.com/img/userinfo.gif){kind=small} vlnv) wrote,@ 2007-03-17 00:21:00 |
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printf style output in VHDL
One very useful package for VHDL is called PCK_FIO, it is available from http://www.easics.com/webtools/freesics
or from LML site: PCK_FIO-2002.7.tar.gz
You need to build the package and library (files PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd).
I have used name printf for the library. Then it's very simple to use:
library std;
use std.textio.all;
library printf;
use printf.pck_fio.all;
architecture ...
file output : text open write_mode is "assertTst.lst";
...
process ...
variable l : line;
...
fprint(output,l, "Tc=%3d ns A=%b B=%b x=%b\n",fo(NOW), fo(A), fo(B),fo(x));
Produces this output:
Tc= 0 ns A=U B=U x=U
Tc= 0 ns A=U B=U x=0
Tc= 0 ns A=0 B=0 x=0
Tc= 1 ns A=0 B=0 x=1
Tc= 1 ns A=0 B=1 x=1
Tc= 1 ns A=1 B=1 x=1
Tc= 2 ns A=1 B=1 x=0
Tc= 2 ns A=0 B=0 x=0
If you need to output to the console, comment out the "file output ... " line (VHDL standard environment has file 'output' already opened as standard output). These common types are supported for output:
std_logic std_ulogic bit
std_logic_vector std_ulogic_vector bit_vector
integer unsigned signed
boolean
character
string
time
One very useful package for VHDL is called PCK_FIO, it is available from http://www.easics.com/webtools/freesics
or from LML site: PCK_FIO-2002.7.tar.gz
You need to build the package and library (files PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd).
I have used name printf for the library. Then it's very simple to use:
library std;
use std.textio.all;
library printf;
use printf.pck_fio.all;
architecture ...
file output : text open write_mode is "assertTst.lst";
...
process ...
variable l : line;
...
fprint(output,l, "Tc=%3d ns A=%b B=%b x=%b\n",fo(NOW), fo(A), fo(B),fo(x));
Produces this output:
Tc= 0 ns A=U B=U x=U
Tc= 0 ns A=U B=U x=0
Tc= 0 ns A=0 B=0 x=0
Tc= 1 ns A=0 B=0 x=1
Tc= 1 ns A=0 B=1 x=1
Tc= 1 ns A=1 B=1 x=1
Tc= 2 ns A=1 B=1 x=0
Tc= 2 ns A=0 B=0 x=0
If you need to output to the console, comment out the "file output ... " line (VHDL standard environment has file 'output' already opened as standard output). These common types are supported for output:
std_logic std_ulogic bit
std_logic_vector std_ulogic_vector bit_vector
integer unsigned signed
boolean
character
string
time
