LML draft for VHDL coding style (standard)
Whereas in C/C++/Perl/Pascal/etc. we have object talking to each other by the way of calling functions/methods, in VHDL we have components talking to each other by the way of signals.

Apparently - entity is same as class (some storage and some inputs (methods) and some output (method return values or globals)).

An instance of an entity is same as class instance - object.

We are trying to base it on our C++ coding standard, therefore:
1. same
2. Class Name --> Entity Name, or Process Name
2a. Architecture name should start with  : RTL, SIM, then optional underscore and specifics
Example: RTL, SIM, RTL_pipelined, RTL_async
3. attributes and operations --> variables
4. constants and labels - UPPER_CASE
6. global variables --> port_names and signal_names. 
6a. use same name if possible for port name and signal connected to that port,
     if collision happens, add _sig suffix to signal name
6b. use _n for active love signal and por names
6c. use port_NAME_n for external ports - i.e. physical ports on the FPGA or ASICs
6d. use clk_ prefix for clocks and rst_ prefix for resets
7-10 same
11. line length limited to 72 chars
12. for entity ports the order:
 a) inputs: clk, rst, enable, address/data, control
b) inputs: same order - clk, rst, enable, address/data, control
c) for multi-section entities - repeat enable/address/data/control sequence for each section
13.  port_name => signal, do not use positional assignments

14. TYPE and SUBTYPE names - UPPERCASE

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Googling on the subject gives several references:
- CS Univ. of Alberta - based on Xilinx coding style
- ALSE-FR coding style

Would love to hear comments.